The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to forming nanosheet transistors having thin and thick gate dielectric material.
In semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors (FETs), can be fabricated on a single wafer. Some non-planar device architectures, such as nanosheet FETs, provide increased device density and can provide increased performance over lateral device architectures. In a known nanosheet FET configuration, the gate wraps around the full perimeter of multiple nanosheet channels in a so-called gate-all-around (GAA) configuration, which enables fuller depletion in the channel regions and reduces short-channel effects due to, for example, steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). The wrap-around gate structures can result in greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.